1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to forming a contact hole in an interlevel dielectric layer.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
Refractory metal silicides are frequently used to provide low resistance contacts for the gate, source and drain. With this approach, a thin layer of refractory metal is deposited over the structure, and heat is applied to form a silicide wherever the refractory metal is adjacent to silicon (including single crystal silicon and polysilicon). Thereafter, an etch is applied that removes unreacted refractory metal to prevent bridging, silicide contacts for the gate, source and drain.
The devices must be selectively interconnected to form circuit patterns. As one approach, a first interlevel dielectric is formed over the substrate, first contact holes (or vias) are etched in the first interlevel dielectric to expose the silicide contacts, first metal plugs are formed in the first contact holes, and a metal-1 pattern is formed over the first interlevel dielectric that selectively interconnects the first metal plugs. Thereafter, a second interlevel dielectric is formed over the metal-1 pattern, second contact holes are etched in the second interlevel dielectric to expose the metal-1 pattern, second metal plugs are formed in the second contact holes, and a metal-2 pattern is formed over the second interlevel dielectric that selectively interconnects the second metal plugs. Additional interlevel dielectrics and metal patterns (such as metal-3, metal-4 and metal-5) can be formed in a similar manner.
Forming contact holes in the first interlevel dielectric is a key step in the fabrication of multilevel interconnect structures. The minimum size of the contact holes is usually determined by the minimum resolution of the optical lithography tool. When contact holes are larger than about 2.0 microns, wet etching is often used. However, the isotropic nature of wet chemical etching makes it generally unsuitable for patterning submicron contact holes. Since the first interlevel dielectric is typically silicon dioxide, dry etching for silicon dioxide is often used to form submicron contact holes.
Dry etching silicon dioxide typically involves a plasma etching procedure in which a plasma generates reactive gas species that chemically etch the material in direct proximity to the plasma. The ability to achieve anisotropic etching requires bombardment of the silicon dioxide with energetic ions. Other parameters such as the chemical nature of the plasma also influence the degree of anisotropy. In general, the etch is highly anisotropic and forms contact holes with straight vertical sidewalls that taper slightly. The etch rate depends on several factors including pressure, power, feed gas composition, and film characteristics. For instance, thermally grown silicon dioxide etches more slowly than chemical vapor deposited silicon dioxide. In addition, the etch can be highly selective of silicon dioxide with respect to underlying silicon.
Dry etch equipment requires the availability of effective end-point detection tools for reducing the degree of overetching, increasing throughput and achieving run-to-run reproducibility. Four common methods for determining the end-point of dry etch processes are 1) laser interferometry and reflectivity, 2) optical emission spectroscopy, 3) direct observation through a viewing port on the chamber by a human operator, and 4) mass spectroscopy. End-point detection of contact holes can be difficult because the total area being etched is quite small compared to other layers.
Furthermore, in many integrated circuits, individual devices in various areas are arranged in different configurations and densities. For example, some integrated circuits include devices having a wide range of functionality with the variability of functionality being reflected in a variability of layout configuration. One implication arising from the variability of configuration is that some areas of the integrated circuit are densely populated with devices while other areas include only relatively isolated devices.
Applicant has observed that when silicon dioxide is dry etched, the etch rate of contact holes is often slower in densely populated areas of the substrate (with a high density of contact holes) than in sparsely populated areas of the substrate (with a low density of contact holes). The difference in etch rates may result from poorly-understood aspects of the chemistry of the plasma etching, such as increasing the rate of reactive ion etching in areas having a low density of contact holes and therefore less of the silicon dioxide layer exposed to the etch. Irrespective of the causes, since etched silicon beneath certain contact holes may be detected before other contact holes are completely etched, an overetch becomes necessary to ensure complete formation of all the contact holes. Unfortunately, the overetching can cause appreciable gouging of the underlying materials beneath the contact holes. For instance, the overetching can damage the silicon surface of source/drain regions, damage or remove thin silicide contacts, remove substantial portions of oxide spacers adjacent to the gate, and/or remove substantial portions of field oxides such as trench oxides or LOCOS in the substrate. The gouging increases the potential for excessive leakage current as well as device failure.
One solution known in the art is to form an interlevel dielectric layer with a thick silicon dioxide layer on a thin silicon nitride layer. A first etch is applied which is highly selective of silicon dioxide with respect to silicon nitride to form holes in the silicon dioxide layer using the silicon nitride layer as an etch stop. This allows the first etch to have a sufficiently long duration without damaging the underlying materials. Thereafter, a second etch is briefly applied which is highly selective of silicon nitride to complete formation of the contact hole. A drawback to this approach, however, is that the second etch is usually highly selective of silicon as well. As a result, substantial damage to an underlying silicon surface may arise.
Accordingly, a need exists for a method of forming a contact hole in an interlevel dielectric without appreciably gouging the underlying materials.